To assure that the induced inversion channel extends all the way from source to drain, the MOSFET gate structure slightly overlaps the edges of source and drain (the latter is achieved by a method known as a self-aligned process. This inversion layer is a conducting channel that connects the two n-type regions at the source and drain it will allow electrons to flow from the source to the drain when there is a positive voltage, VDS, between the source and drain. Further increases in VGS attract electrons from the electron-rich source (VGS) and drain (VGD) regions into the region under the gate, producing an n+ region known as the “inversion layer”, shown in Figure 3(b). When VGS reaches a threshold value (VTH, the minimum gate to source voltage needed to turn the device on this is less than the 0.7 V required in BJTs, typically 0.2-0.25 V in modern logic processors), the region under the gate becomes completely depleted of charge, producing a region in the substrate called the “depletion zone”. When a small voltage, (VGS) is applied to the gate, the charge carrying holes in the p-type substrate are repelled away from the substrate surface. In operation, the potential between the drain and source (VDS), and that between the gate and source (VGS), are always positive. Two P-N junctions exist between the n-type source/drain regions and the bulk p-type substrate. Figure 3(a) shows the device in the “Off” state with the gate, source and drain voltages at zero and the bulk substrate connected to ground. The operational characteristics of an nMOSFET transistor are shown in Figure 2 basic operating principles of a MOSFET device can be explained within the context of an NMOS device as shown in Figure 3. Finally, a conducting gate material, either a metal or highly doped polysilicon, is deposited on top of the gate oxide, creating the three-terminal device structure shown in Figure 1. A very thin insulating oxide layer covers the channel region it is commonly referred to as a gate oxide. The bulk material between the source and drain in a MOSFET is called the channel. This situation is reversed in a PMOS device, as shown in Figure 1(b). An NMOS device is built on a p-doped silicon substrate that has had regions of n-type material which are created using ion implantation, as shown in Figure 1(a).These n-type regions are called the source and the drain. The majority of carriers in NMOS devices are electrons while those in PMOS devices are holes. MOSFETs can be built as either NMOS or PMOS transistors, depending on the polarities of the bulk, source and drain regions as shown in Figure 1. Figure 1 shows the elements of a typical MOSFET where the transistor is built into the surface of a silicon bulk substrate. Since MOSFETs are the most widely used FET, we will use these devices to describe the components and operation of this class of transistor. FETs differ from BJTs in the way that current flow through the device is controlled the primary current flow through an FET is controlled by a small voltage applied to one of the terminals rather than by a control current flow through any part of the device. Indeed, MOSFET devices constitute the ubiquitous “bit” switch that is set to 0 (“Off” state) or 1 (“On” state) in microelectronic logic devices (i.e., computers). FETs can replace BJTs in most electronic circuits and have advantages for use in microelectronics since they consume and dissipate less power and they can be made much smaller than equivalent BJTs. MOSFETs are planar surface devices that are the most commonly used variant of Field Effect Transistors (FETs) the reader may also encounter Junction Gate Field Effect Transistors (JFETs) and Insulated Gate Field Effect Transistors (IGFETs). Another very common form of transistor is the Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
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